Design methodology for millimeter-wave low-noise amplifiers.

This thesis describes a systematic design methodology for millimeter-wave, low noise amplifiers (LNAs). It focuses on the inductively--leaded SiGe HBT cascodc LNA topology. Three LNAs operating at 50 and 65 GHz are fabricated in 0.18mum SiGe BiCMOS technology to validate the proposed methodology. The measured LNA performance agrees well With simulations and is close to the theoretical limit in the given technology. Several of the LNA low-noise design techniques are applied to the design of a 65-GHz receiver integrating an LNA, a down-conversion mixer, a full-rate VCO, and an IF amplifier. The fabricated receiver has a gain of 24 dB and a noise figure of 12 dB. Using compact on-chip inductors, the IC occupies an area of 0.6 mm2, several times smaller than similar published receivers. To the best of the author's knowledge, it is the first millimeter-wave silicon receiver to integrate the VCO on-chip.